1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more specifically, to a technology of processing external commands in parallel using divided clocks, thereby embodying a high-speed operation of a DRAM in increase of clock frequency.
2. Background of the Prior Art
FIG. 1 is a diagram illustrating a conventional semiconductor memory device.
The conventional semiconductor memory device comprises a clock generator 1, an input buffer 2, a latch unit 3, a command processing block 4, a bank control block 5 and an asynchronous block 6.
The clock generator 1 generates an internal clock CLKP synchronously with respect to a clock CLK applied externally. The input buffer 2 compares a reference voltage Vref with a command signal CMD applied externally, and outputs a signal having a full voltage level to a node ND1.
The latch unit 3 latches an output signal from the node ND1 Synchronously with respect to a first internal clock CLKP applied from the clock generator 1, and outputs the latched output signal to a node ND2. The latch unit 3 Latches data applied to the node ND1 during a pulse width period of the first internal clock CLKP.
The command processing block 4 latches an output signal from the node ND2 synchronously with respect to a second internal clock CLKP, and outputs the latches output signal to a node ND3. The bank control block 5 latches an output signal from the node ND3 synchronously with respect to a third internal clock CLKP, and outputs the latches output signal to the asynchronous block 6. The asynchronous block 6 performs a specific processing by internal sequential asynchronous operation in response to an output signal applied from a node ND4.
The above-described conventional semiconductor memory device uses the externally applied clock CLK or alters the clock CLK to have a predetermined pulse width, thereby controlling internal command processing blocks.
However, if internal command processing blocks use the externally inputted clock CLK as it is when the frequency of the clock CLK increases over 1 GHz at high-speed operation of the conventional semiconductor memory device, the internal command processing blocks do not secure the normal operation.
That is, the data processing time of more than 1 ns is required so that each of the command processing block 4 and the bank control block 5 may perform a normal operation. However, when the frequency of the clock CLK is more than 1 GHz, the data processing time is not sufficient in transmission of a signal latched in the command processing block 4 to the bank control block 5, and the conventional semiconductor memory device do not perform the normal operation.